1. Field of the Invention
The present invention relates to a complementary signal generating circuit, and more particularly to a complementary signal generating circuit generating an in-phase signal and a reverse phase signal.
2. Description of Related Art
Up to now, there has been known a complementary signal generating circuit for generating a complementary signal composed of an in-phase signal that is a signal in phase with an input signal and a reverse phase signal that is 180° out of phase with an input signal. The complementary signal is used in a LVDS (Low Voltage Differential Signals) circuit or a memory drive circuit. As these circuits have increased their operational speeds in recent years, a demand for a technique of generating a complementary signal with higher precision grows.
FIG. 9 is a circuit diagram of the configuration of a conventional complementary signal generating circuit 900. As shown in FIG. 9, in the conventional complementary signal generating circuit 900, inverters 901 and 902 are connected in series. Further, a transfer gate 903 is connected with an intermediate node between the inverters 901 and 902. When an input signal Sin is input to the inverter 901 from an the input terminal IN, the inverter 902 sends an in-phase signal Strue to a terminal TRUE, and a reverse phase signal Sbar is sent to a terminal BAR from the transfer gate 903.
In the conventional complementary signal generating circuit 900, the transfer gate 903 gives a delay to the reverse phase signal Sbar in order to reduce a difference in delay between the in-phase signal Strue and the reverse phase signal Sbar. Thus, in the conventional complementary signal generating circuit 900, the circuit configuration differs between an output stage for the in-phase signal Strue and an output stage for the reverse phase signal Sbar.
FIG. 10 is a circuit diagram of the configuration of a conventional complementary signal generating circuit 910 disclosed in Japanese Unexamined Patent Publication No. 3-258015. As shown in FIG. 10, in the conventional complementary signal generating circuit 910, a P-channel MOS transistor 911 and an N-channel MOS transistor 912 are connected in series. Further, an N-channel MOS transistor 913 and a P-channel MOS transistor 914 are connected in series. When an input signal Sin is input to each gate of the MOS transistors 911 to 914 from an the input terminal IN, a reverse phase signal Sbar is output to a terminal BAR from an intermediate node between a P-channel MOS transistor 911 and an N-channel MOS transistor 912. Further, an in-phase signal Strue is output to a terminal TRUE from an intermediate node between an N-channel MOS transistor 913 and a P-channel MOS transistor 914.
In the conventional complementary signal generating circuit 910, an output stage for the reverse phase signal Sbar is set to an inverter configuration, and an output stage for the in-phase signal Strue is set to a source follower configuration. In this way, a difference in delay between the in-phase signal Strue and the reverse phase signal Sbar is minimized. Thus, in the conventional complementary signal generating circuit 910, the circuit configuration differs between the output stage for the in-phase signal Strue and the output stage for the reverse phase signal Sbar.
FIG. 11 is a circuit diagram of the configuration of a conventional signal generating circuit as disclosed in Japanese Unexamined Patent Publication No. 2002-368602. This conventional signal generating circuit 800 generates a desired complementary signal by means of a conventional complementary signal generating circuit 920 and a level shifting circuit 30.
In the conventional complementary signal generating circuit 920, inverters 921 and 922 are connected in series. If an input signal Sin is input from the input terminal IN to the inverter 921, a reverse phase signal Sbar is output from the inverter 921 to a terminal BAR, and an in-phase signal Strue is output from the inverter 922 to a terminal TRUE.
The level shifting circuit 30 includes a flip-flop 100, and output circuits 110 and 120. In the flip-flop 100, P-channel MOS transistors P101 and P102 and an N-channel MOS transistor N101 are connected in series. Further, P-channel MOS transistors P103 and P104 and an N-channel MOS transistor N102 are connected in series. A gate of the P-channel MOS transistor P101 is connected with an intermediate node between the P-channel MOS transistor P104 and the N-channel MOS transistor N102. A gate of the P-channel MOS transistor P103 is connected with an intermediate node between the P-channel MOS transistor P102 and the N-channel MOS transistor N101.
In the output circuit 110, a P-channel MOS transistor P111 and an N-channel MOS transistor N111 are connected in series. In the output circuit 120, a P-channel MOS transistor P121 and an N-channel MOS transistor N121 are connected in series.
An in-phase signal Strue from the conventional complementary signal generating circuit 920 is input to each gate of the P-channel MOS transistor P102 and the N-channel MOS transistor N101. In addition, a reverse phase signal Sbar is input to each gate of the P-channel MOS transistor P104 and the N-channel MOS transistor N102.
If an in-phase signal Strue from the conventional complementary signal generating circuit 920 is at High level, a gate potential of the N-channel MOS transistor N101 increases, and a reverse phase signal S110 is shifted to Low level. Then, a gate potential of the P-channel MOS transistor P103 lowers, and an in-phase signal S120 is shifted to High level.
If a reverse phase signal Sbar from the conventional complementary signal generating circuit 920 is at High level, a gate potential of the N-channel MOS transistor N102 increases, and the in-phase signal S120 is shifted to Low level. Then, a gate potential of the P-channel MOS transistor P101 lowers, and a reverse phase signal S110 is shifted to High level.
The output circuit 110 inverts the reverse phase signal S110 to output an in-phase signal Strue2. The output circuit 120 inverts the in-phase signal S120 to output a reverse phase signal Sbar2.
In the conventional complementary signal generating circuit 920, a delay is given to the in-phase signal Strue by the inverter 922. The level shifting circuit 30 is provided this way in order to minimize a difference in delay between the in-phase signal Strue and the reverse phase signal Sbar.
In addition, a circuit disclosed in Japanese Unexamined Patent Publication No. 2003-198343 has been known as another conventional complementary signal generating circuit. In the circuit disclosed in Japanese Unexamined Patent Publication No. 2003-198343, an output signal is fed back to adjust a timing of a complementary signal with an inverting circuit such as an operational amplifier.
As described above, in the conventional complementary signal generating circuit 900 or 910 of FIGS. 9 and 10, the circuit configuration differs between the output stage for the in-phase signal and the output stage for the reverse phase signal, resulting in a problem that a through rate difference or difference in delay between the in-phase signal and the reverse phase signal is large, and an influence of production tolerance is also large.